2017 Poster Sessions : Carbon Nanotubes Enable Major Energy Efficiency Benefits for sub-10 nm Node Digital VLSI Circuits

Student Name : Gage Hills
Advisor : Subhasish Mitra
Research Areas: Computer Systems
While scaling of silicon-based field-effect transistors (FETs) has significantly improved digital logic circuit speed and energy efficiency for decades, continued miniaturization yields diminishing returns. How can we then achieve the next order of magnitude improvement in energy efficiency of digital logic technologies? To address this outstanding question, a variety of technology options are currently being explored for future sub-10 nm nodes (e.g., the 7 nm node). These options include silicon-based evolutionary developments – such as silicon-germanium (SiGe) channels, extremely-thin silicon-on- insulator (ETSOI) or progressing from FinFETs to nanowires (NWs) – as well as replacing silicon with nanotechnologies such as carbon nanotube FETs (CNFETs). To effectively guide the exploration of such options, the following question must also be answered: how do we accurately compare the energy efficiency benefits of these technology options for realistic very-large-scale integrated (VLSI) logic circuits? Here, we answer both questions. 1) We quantify and compare the VLSI circuit-level energy efficiency benefits (quantified by the energy-delay-product: EDP) for all of these future technology options, using industry-standard physical designs of sub-10 nm node digital VLSI processors, and using technology parameters extracted from experimental data. 2) We demonstrate that compared with sub-10 nm FinFETs, evolutionary silicon-based technologies offer only marginal (<30%) EDP benefits. In contrast, CNFETs drastically improve EDP of VLSI digital logic circuits by an order of magnitude (9.0X), while maintaining the same off-state leakage current density (≤100 nA per micron of FET width) and total chip power density (≤100 W per cm2 of chip area).

Gage Hills is a PhD candidate in Electrical Engineering at Stanford University, advised by Professor Subhasish Mitra and co-advised by Professor Philip Wong. He received the M.S. Degree in Electrical Engineering from Stanford in 2012, and the B.S. Degree in Electrical Engineering & Computer Science from Yale University in 2007. From 2007 to 2010, he worked on the development of time-of-flight cameras, first at Canesta, Inc., in Sunnyvale, CA, and then at Microsoft, in Mountain View, CA, where he holds two patents. In 2014, he worked at Intel, in Hillsboro, Oregon, in the Circuits Research Laboratory, developing hardware accelerators using Intel’s 14 nm technology node PDKs. In 2015, he worked at IMEC, in Leuven, Belgium, under the supervision of Francky Catthoor and Praveen Raghavan, leveraging IMEC’s physical design tools and PDKs to evaluate and design digital VLSI circuits using carbon nanotubes at sub-10 nm technology nodes. His research highlights include the development of techniques for rapid co-optimization of processing and circuit design to overcome variations in carbon nanotube circuits; this work was nominated for a best paper award at the Design Automation Conference (DAC) in 2013. He also contributed to the development of the first digital sub-systems built entirely using carbon nanotube FETs (ISSCC, 2013), and to the demonstration of the first carbon nanotube computer, which was highlighted on the cover of Nature in Sept. 2013.