2017 Poster Sessions : Exploiting a Natural Network Effect for Scalable, Fine-grained Clock Synchronization

Student Name : Yilong Geng, Shiyu Liu, Zi Yin
Advisor : Balaji Prabhakar
Research Areas: Information Systems
Nanosecond-level clock synchronization can be an enabler for a new spectrum of timing- and
delay-critical applications in data centers. However, widely deployed clock synchronization
algorithms can only achieve millisecond level precision. Current solutions for achieving synchronization
precision of 10s-100s of nanoseconds require specially designed hardware throughout the network to
combat random network delays and component noise or to exploit clock synchronization inherent in
Ethernet standards for the PHY.

In this paper, we present ConcertClocks, a software clock synchronization system that leverages a synchronization network around three key ideas. First, coded probes identify and reject impure probe data---data captured by probes which suffer queueing delays, random jitter, and NIC timestamp noise. Next, ConcertClocks processes the purified data with Support Vector Machines, a widely used and powerful classifier, to accurately estimate one-way propagation times and achieve clock synchronization to within 100 nanoseconds. Finally, ConcertClocks exploits a natural network effect---the idea that a group of pair-wise synchronized clocks must be transitively synchronized---to detect and correct synchronization errors even further.

Through evaluation of two real hardware testbeds, we quantify the imprecision of existing clock synchronization across server-pairs, and the effect of temperature on clock speeds. We find the discrepancy between clock frequencies is typically 5-10us/sec, but it can be as much as 30us/sec. We show that ConcertClocks achieves synchronization to within a few 10s of nanoseconds under varying loads, with a negligible overhead upon link bandwidth due to probes. Because ConcertClocks is implemented in software running on standard hardware, it is ready for deployment in current data centers.

Shiyu Liu is a 2nd year Ph.D. student in Electrical Engineering Department, Stanford University. Shiyu’s current research topic is inference and learning in Data Center Networks, primarily focusing on high fidelity reconstruction algorithms. Before that he worked on wireless networks, including projects on congestion control in Wi-Fi and intelligent client device sensing with Zigbee. He received his undergraduate degree in Electronic Engineering from Tsinghua University in 2015.

Zi Yin is a 4th year Ph.D. student, Electrical Engineering, Stanford University. Zi’s current research is on applying Machine Learning techniques to problems in Cloud and Data Centers. In the past, he worked on deep learning and its application in natural language processing, in particular sequence-to-sequence models for query relevance scoring. He has abundant experience in statistics and machine learning theory. Zi received his bachelor degrees in Mathematics and Information Engineering from Chinese University of Hong Kong.

Yilong Geng is a 5th year Ph.D. student, Electrical Engineering, Stanford University. Yilong’s research interest is in data center networking, from new hardware architectures to use of machine learning techniques. Currently, he’s designing algorithms and a scalable system for high fidelity network reconstruction and clock synchronization, all based on data from edge measurements. Prior to that, he worked on several NetFPGA projects, including Open Source Network Tester (OSNT) and a new NIC architecture for scalable end-host rate limiting. He received his undergraduate degree in Electronic Engineering from Tsinghua University.