2010 Poster Sessions : Enabling Technology for On-Chip Networks

Student Name : George Michelogiannakis
Advisor : William Dally
Research Areas: Computer Systems
Abstract:
Technology scaling has enabled the design of chips that integrate hundreds of functional blocks. Networks-on-chip (NoCs) have been developed to facilitate communication between different blocks in such highly parallel designs. However, state-of-the-art NoC implementations frequently account for as much as 40% of a chip's total power budget. In our work, we are developing enabling technology for efficient NoCs by exploiting the on-chip environment. We are taking a bottom-up approach by investigating all networks layers and using the trade offs from one layer to influence design decisions in the next. We have developed efficient low-swing channels and crossbars which consume 6x and 5x less energy per bit compared to full-swing circuitry, respectively. Furthermore, we have proposed the flattened butterfly topology which provides direct connectivity between routers in each dimension. Flattened butterfly networks provide higher throughput than current topologies for the same amount of power. Moreover, we have proposed elastic buffer flow control which uses the existing channel pipeline flip-flops for buffering in place of expensive input buffers at the routers. The associated area and power improvements can be traded for a wider datapath to increase performance. Finally, we have investigated the microarchitectural tradeoffs of virtual-channel routers. We have found that the choice of VC allocator has minimal impact on network performance, and that wavefront-based switch allocators can be employed to improve matching at the cost of slightly increased cycle time.

Bio:
George Michelogiannakis is a third year Ph.D. candidate working with Prof. Dally. His research focuses on networks-on-chip (NoCs) as well as multi-core systems and systems-on-chip. His recent research contributions are a novel flow-control technique for NoCs, a thorough evaluation of bufferless flow control, as well as co-designing NoCs with the cache hierarchy and coherency protocol.