2011 Poster Sessions : Enabling Technology for On-Chip Networks

Student Name : Nan (Ted) Jiang
Advisor : William Dally
Research Areas: Computer Systems
Future large-scale chip multiprocessors will rely on sophisticated on-chip interconnection networks to provide efficient core-to-core communication. These networks must provide high throughput at low latency while meeting stringent power and area constraints. Our research is focusing on the development of enabling technology for such on-chip networks in terms of both circuits and network architecture. On the circuit level, we are designing energy efficient network building blocks such as channels, buffers, and crossbars switches. At the architectural level, we are investigating numerous aspects of the network including topology, flow control techniques, routing algorithm, routing micro-architecture, and network quality of service.

Nan Jiang is currently a fourth year PhD student in the electrical engineering department. He has worked in professor Bill Dally's Concurrent VLSI Architecture group for the past four years studying interconnection networks. His research projects have included exploring energy efficient topologies for on-chip networks, studying the effects of age-based fairness for on-chip networks, designing adaptive routing algorithms for supercomputing networks, and evaluating implementations of high radix routers for supercomputing networks.