2012 Poster Sessions : Effective Post-Silicon Validation

Student Name : David Lin
Advisor : Subhasish Mitra
Research Areas: Computer Systems
Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture. Due to sheer design complexity, it is nearly impossible to detect and fix all bugs before manufacture. Existing post-silicon validation methods barely cope with today’s complexity. New techniques are essential to minimize the effects of bugs and design flaws going forward. This talk will focus on a recent technique, QED, that can overcome significant post-silicon validation challenges. We demonstrate the effectiveness of QED using results from multiple hardware platforms (quad-core Intel Core i7 processors and the 48-core Intel Single-Chip Cloud Computer).

David Lin received his B.S. in Electrical Engineering from
California Institute of Technology. Currently, he is a third year Ph.D. student in Electrical Engineering at Stanford University. His research interests include computer architecture, post-silicon validation, and robust systems design.