2013 Poster Sessions : Quick Error Detection for Effective Post-Silicon Validation of System-on-Chips

Student Name : David Lin
Advisor : Subhasish Mitra
Research Areas: Computer Systems
Abstract:
We present a technique for systematically creating post-silicon validation tests, called Quick Error Detection (QED) tests, that quickly detect bugs in processor cores and uncore components of multi-core System-on-Chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation approaches. We present experimental results from a quad-core Intel® Core™ i7 hardware platform and simulation results for a complex OpenSPARC T2-like SoC with “difficult” bug scenarios that occurred in commercial multi-core SoCs. Our results demonstrate: 1. Error detection latencies of “typical” post-silicon validation tests can be up to billions of clock cycles 2. Our QED technique shortens error detection latencies by several orders of magnitude. 3. Our QED technique enables 2- to 4-fold increase in bug coverage. QED does not require any hardware modification and is readily applicable to existing designs.

Bio:
David Lin is a Ph.D. student in the Robust Systems Group. His research interests include validation, verification, computer architecture, and robust systems.