2013 Poster Sessions : Network Interface Design for Low Latency Request-Response Protocols

Student Name : Mario Flajslik
Advisor : Mendel Rosenblum
Research Areas: Computer Systems
Ethernet network interfaces in commodity systems are designed with a focus on achieving high bandwidth at low CPU utilization, with latency as a secondary issue. Latency is often overwhelmingly dominated by software packet processing, justifying this approach. A recent push for low software latency in request-response based systems that run on commodity hardware, such as memcached and RAMCloud, has promoted network interface latency into a significant, if not dominating, fraction of the overall latency. In this poster, we present a network interface design that provides low latency by concentrating on the request-response nature of protocols in use, in particular the observation that, often, over half of the packets are very small in size. For small packets, our design minimizes the number of PCIe transitions, which are a major source of latency, and for bigger packets we employ a refined DMA approach. We also consider latency impacts of CPU idle states, CPU performance states, use of interrupts, different methods of polling, as well as hardware components such as MAC and PHY. Evaluation on a prototype FPGA implementation has demonstrated that our design exhibits over 2X latency improvements without a meaningful negative impact on either bandwidth or CPU power.

Mario is a Electrical Engineering PhD student working with professor Rosenblum. His research interests include computer architecture and computer networking, particularly low latency I/O and how it interacts with the OS. Mario received his MS degree from Stanford University and his undergraduate degree from University of Zagreb, Croatia.