2016 Poster Sessions : A 220pJ_Pixel_Frame CMOS Image Sensor with Partial Settling Readout Architecture

Student Name : Suyao Ji
Advisor : Mark Horowitz
Research Areas: Computer Systems
Abstract:
To reduce power consumption in a CMOS imager readout path, we use partial settling of the column values into a SAR-ADC, creating a 320Hx240V prototype sensor with two column-shared 10-bit ADCs, which totally consumes 2.2mW at 130 fps. The measured INL and DNL with a third order correction of partial settling behavior is +1.855LSB/-1.855LSB and +0.337LSB/-0.179LSB, respectively. The input referred readout noise is 5e- with a conversion gain of 90uV/e-.

Bio:
Suyao Ji is a PhD candidate at Electrical Engineering Department of Stanford University. She received her BS in Electrical Engineering from Caltech in 2011. Her research interests include power efficient analog/mixed-signal circuit design, and CMOS image sensor design. She is currently working on designing a low power imager for computational photography.