2016 Poster Sessions : Generating Configurable Hardware from Parallel Patterns

Student Name : Raghu Prabhakar
Advisor : Oyekunle Olukotun
Research Areas: Computer Systems
Abstract:
In recent years the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising for the implementation of these accelerators, as they offer significant performance and energy improvements over CPUs for a wide class of applications and are far more flexible than fixed-function ASICs. However, FPGAs are difficult to program. Traditional programming models for reconfigurable logic use low-level hardware description languages like Verilog and VHDL, which have none of the productivity features of modern software languages but produce very efficient designs, and low-level software languages like C and OpenCL coupled with high-level synthesis (HLS) tools that typically produce designs that are far less efficient. Functional languages with parallel patterns are a better fit for hardware generation because they provide high-level abstractions to programmers with little experience in hardware design and avoid many of the problems faced when generating hardware from imperative languages. In this paper, we identify two important optimizations for using parallel patterns to generate efficient hardware: tiling and metapipelining. We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines. We demonstrate experimentally that these optimizations result in speedups up to 39.4× on a set of benchmarks from the data analytics domain.

Bio:
Raghu Prabhakar is a third year PhD student advised by Prof. Kunle Olukotun and Prof. Christos Kozyrakis. His research interests span the areas of computer systems architecture, compilers, and domain-specific languages. His current focus is on reconfigurable architectures and associated compilation techniques from high-level languages. Raghu received his B.E. from RV College of Engineering, Bangalore, India, and his M.S. from the University of California, Los Angeles.