2008 Poster Sessions : Low-Power Routing Fabric in FPGA

Student Name : Mingjie Lin
Advisor : Abbas El Gamal
Research Areas: Information Systems
Abstract
This paper describes a new programmable routing fabric and shows that an FPGA that uses this fabric can achieve 1.54 times lower dynamic power consumption and 1.31 times lower average net delays with only 8% reduction in logic density over a baseline island-style FPGA implemented in the same 65nm CMOS technology. These improvements in power and delay are achieved by (i) using only short interconnect segments to reduce routed net lengths, and (ii) reducing interconnect segment loading due to programming overhead relative to the baseline FPGA without compromising routability. The new routing fabric is well-suited to monolithically stacked 3D-IC implementation. It is shown that a 3D-FPGA using this fabric can achieve a 3.3 times improvement in logic density, a 2.46 times improvement in delay, and a 2.87 times improvement in dynamic power consumption over the same baseline 2D-FPGA.

Bio
Mingjie Lin (S'01) received the B.S. from Xi'an Jiaotong University, Xi'an, China, in 1993, and the M.S. degree in mechanical engineering and electrical engineering from Clemson University, Clemson, SC, in 2001. He is currently working toward the Ph.D. degree at the Department of Electrical Engineering, Stanford University, Stanford, CA.

His research interests include next-generation FPGA architectures as part of a DARPA-funded project with the Center of Integrated System.