2008 Poster Sessions : Stanford Chip Genertor Project

Student Name : Zain Asgar
Advisor : Mark Horowitz
Research Areas: Computer Systems
Abstract
The integrated circuit industry faces a huge challenge as we enter the post 90nm generation. Poor scaling makes power efficiency critical, which necessitates application optimized chips. Unfortunately the high cost of chip design forces the industry to move in the opposite direction, toward a set of generic programmable solutions that are optimized only for a broad application class. We argue that these flexible, general computing chips are trying to accomplish more than is commercially needed. Since design NRE costs are an order of magnitude larger than fabrication NRE costs, a two-step design system seems attractive. First, the users configure a flexible computing framework to run their application with the desired performance. Then, the system "compiles" the configuration, tailoring the original framework to create a chip that is optimized toward the desired application set. This approach achieves the best of both worlds: it combines the reduced development costs associated with a flexible solution with the efficiency of a custom chip.

Bio
Zain Asgar received his undergraduate degrees in Electrical and Computer Engineering at the University of Minnesota with Summa Cum Laude and High Distinction. He is currently pursuing his PhD under Prof. Mark Horowitz at Stanford University in the area of chip multi-processors. He has worked at PMC-Sierra on ASIC design. He is currently working at NVIDIA Corporation on the design of next generation graphics processors.